Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers) have migrated to deep sub-micron process nodes due to cost and power consumption considerations. The design complexity of mobile RF transceivers is further complicated by added circuit function to support communication enhancements. Further design challenges for mobile RF transceivers include analog/RF performance considerations, such as mismatch, noise, and other performance considerations. The design of these mobile RF chips includes the use of a phase locked loop (PLL), for example, to generate an output signal with a phase related to a phase of an input signal.
A PLL enables a closed-loop frequency control system that is based on a phase difference between the input clock signal and a feedback clock signal of a controlled oscillator. The main blocks of the PLL are a phase frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO), and counters. These counters may include a feedback counter (M), a pre-scale counter (N), and a post-scale counter (C).
Conventional, area-efficient phase locked loop architectures may employ a sampled-data approach with separate integral and proportional controls. The separate integral and proportional controls provide a way to stabilize the loop. In addition, alternating reference clock phases are used to ease settling constraints of different phases.
In practice, some issues arise with implementation of the area-efficient PLL architecture, such as in reducing a zero frequency (w_zero). In particular, if an integral current (Ipi) is too small, matching and speed may suffer. By contrast, increasing a proportional current (Ipp) may result in higher loading and power consumption issues. Reducing the zero frequency is a significant challenge in the area-efficient PLL architecture.